library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity stack is
    Port ( clk 	   : in  STD_LOGIC;       
	   operation      : in  STD_LOGIC;
	   enable       : in  STD_LOGIC;        
	   d_in    : in  STD_LOGIC_VECTOR (9 downto 0);
		d_out   : out STD_LOGIC_VECTOR (9 downto 0));
end stack;

architecture RTL of stack is
	type stack is array (0 to 7) of std_logic_vector(9 downto 0);

	signal stk : stack;

	begin
		process (clk)
		
		--Puntero de pila
		variable stk_pointer : Integer;
		begin
			--
			if rising_edge (clk) then
				if enable = '1' then							
					if operation = '1' then -- write
						stk(conv_integer(stk_pointer)) <= d_in;
						--Control desbordamiento de pila
						if (stk_pointer = 7) then
							stk_pointer := 0;
						else
							stk_pointer := stk_pointer + 1;
						end if;
						--Fin control desbordamiento pila
						
					else --read
						--Control base pila
						if (stk_pointer = 0) then
							stk_pointer := 7;
						else
							stk_pointer := stk_pointer - 1;
						end if;
						--Fin control base
						d_out <= stk(conv_integer(stk_pointer));
					end if;
				end if;
			end if;
		end process;
end RTL;

